Hardware-Software Co-Design for Efficient Deep Learning Acceleration

Authors

  • Jyothi Swaroop Arlagadda Independent Researcher
  • Suresh dodda Independent Researcher
  • Navin Kamuni Independent Researcher

Abstract

 Deep learning has revolutionized various fields, from computer vision to natural language processing. However, the computational demands of deep learning algorithms have necessitated the development of specialized hardware accelerators. This paper reviews the advancements in hardware accelerators designed for deep learning, focusing on GPUs, TPUs, FPGAs, and custom ASICs. It discusses their architectures, performance metrics, and trade-offs. Additionally, the paper explores emerging trends and future directions in hardware acceleration for deep learning.

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Published

2023-02-11

How to Cite

Arlagadda, J. S., dodda, S., & Kamuni, N. (2023). Hardware-Software Co-Design for Efficient Deep Learning Acceleration. MZ Computing Journal, 4(1). Retrieved from http://mzresearch.com/index.php/MZCJ/article/view/212